Renesas RL78/G15 - Page 184

RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 184 of 765
Mar 7, 2023
Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/5)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 2, 4, 6
)
CKSm
n1
CKSm
n0
0
CCSm
n
MAST
ERmn
STSmn
2
STSmn
1
STSmn
0
CISmn
1
CISmn
0
0 0
MDmn
3
MDmn
2
MDmn
1
MDmn
0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 1, 3)
CKSm
n1
CKSm
n0
0
CCSm
n
SPLIT
mn
STSmn
2
STSmn
1
STSmn
0
CISmn
1
CISmn
0
0 0
MDmn
3
MDmn
2
MDmn
1
MDmn
0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 0, 5, 7
)
CKSm
n1
CKSm
n0
0
CCSm
n
0
Note 1
STSmn
2
STSmn
1
STSmn
0
CISmn
1
CISmn
0
0 0
MDmn
3
MDmn
2
MDmn
1
MDmn
0
CKSmn
1
CKSmn
0
Selection of operation clock (f
MCK
) of channel
0 0 Operation clock CKm0 set by timer clock select register m (TPSm)
0 1 Operation clock CKm2 set by timer clock select register m (TPSm)
1 0 Operation clock CKm1 set by timer clock select register m (TPSm)
1 1 Operation clock CKm3 set by timer clock select register m (TPSm)
Operation clock (f
MCK
) is used by the edge detector. A count clock (f
TCLK
) and a sampling clock are generated depending
on the setting of the CCSmn bit.
The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3.
CCSmn Selection of count clock (f
TCLK
) of channel n
0 Operation clock (f
MCK
) specified by the CKSmn0 and CKSmn1 bits
1 Valid edge of input signal input from the TImn pin
●
In channel 1, valid edge of input signal selected by ISC
Count clock (f
TCLK
) is used for the counter, output controller, and interrupt controller.
Note 1. Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.
Caution 1. Be sure to clear bits 13, 5, and 4 to 0.
Caution 2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for f
CLK
is changed (by
changing the value of the system clock control register (CKC)), even if the operation clock (f
MCK
)
specified by using the CKSmn0 and CKSmn1 bits or the valid edge of the signal input from the
TImn pin is selected as the count clock (f
TCLK
).
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)