RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 285 of 765
Mar 7, 2023
Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used
(Output Two Types of PWMs) (1/2)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmp
CKSm
p1
CKSm
p0
CCSm
p
M/S
Note 1
2
1
0
CISmp
1
CISmp
0
MDmp
3
MDmp
2
MDmp
1
MDmp
0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmq
CKSm
q1
CKSm
q0
CCSm
q
M/S
Note 1
2
1
0
CISmq
1
CISmq
0
MDmq
3
MDmq
2
MDmq
1
MDmq
0
1/0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp and TImq pins input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmp and MASTERmq bits (channels 2, 4, 6)
0: Slave channel
Setting of SPLITmp and SPLITmq bits (channels 1, 3)
0: 16-bit timer mode
Count clock selection
0: Selects operation clock (f
MCK
).
Operation clock (f
MCK
) selection
00B: Selects CKm0 as operation clock of channel p, q.
10B: Selects CKm1 as operation clock of channel p, q.
* Make the same setting as master channel.
Note 1. TMRm2, TMRm4, TMRm6: MASTERmp, MASTERmq bit
TMRm1, TMRm3: SPLITmp, SPLITmq bit
TMRm5, TMRm7: Fixed to 0
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are integers greater than n)
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