RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 286 of 765
Mar 7, 2023
Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used
(Output Two Types of PWMs) (2/2)
(b) Timer output register m (TOm)
Bit q Bit p
TOm TOmq
TOmp
0: Outputs 0 from TOmp or TOmq.
1: Outputs 1 from TOmp or TOmq.
1/0 1/0
(c) Timer output enable register m (TOEm)
Bit q Bit p
TOEm
TOEm
q
TOEm
p
0: Stops the TOmp or TOmq output operation by counting operation.
1: Enables the TOmp or TOmq output operation by counting operation.
1/0 1/0
(d) Timer output level register m (TOLm)
Bit q Bit p
TOLm
0: Positive logic output (active-high)
1: Negative logic output (active-low)
1/0 1/0
(e) Timer output mode register m (TOMm)
Bit q Bit p
TOMm
TOMm
q
TOMm
p
1: Sets the slave channel output mode.
1 1
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are integers greater than n)
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