RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 287 of 765
Mar 7, 2023
Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (1/3)
Software Operation Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register
is disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
default
setting
Sets timer mode registers mn, mp, mq (TMRmn,
TMRmp, TMRmq) of each channel to be used
(determines operation mode of channels).
An interval (period) value is set to timer data register
mn (TDRmn) of the master channel, and a duty factor
is set to the TDRmp and TDRmq registers of the slave
channels.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets slave channel.
The TOMmp and TOMmq bits of timer output
mode register m (TOMm) are set to 1 (slave
channel output mode).
Sets the TOLmp and TOLmq bits.
Sets the TOmp and TOmq bits and determines
default level of the TOmp and TOmq outputs.
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the
port register is 0.
Sets the TOEmp and TOEmq bits to 1 and enables
operation of TOmp and TOmq.
Clears the port register and port mode register to
0.
TOmp and TOmq do not change because channels
stop operating.
The TOmp and TOmq pins output the TOmp and
TOmq set levels.
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
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