RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 288 of 765
Mar 7, 2023
Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (2/3)
Software Operation Hardware Status
Operation is resumed.
Operation
start
(Sets the TOEmp and TOEmq (slave) bits to 1 only
when resuming operation.)
The TSmn bit (master), and TSmp and TSmq (slave)
bits of timer channel start register m (TSm) are set to
1 at the same time.
The TSmn, TSmp, and TSmq bits automatically
return to 0 because they are trigger bits.
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting,
INTTMmn is generated. Triggered by this interrupt,
the slave channel also starts counting.
During
operation
Set values of the TMRmn, TMRmp, TMRmq registers,
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and
TOLmq bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq
registers can be changed after INTTMmn of the
master channel is generated.
The TCRmn, TCRmp, and TCRmq registers can
always be read.
The TSRmn, TSRmp, and TSRmq registers are not
used.
Master channel loads the value of the TDRmn register
to timer count register mn (TCRmn), and the counter
starts counting down. When the count value reaches
TCRmn = 0000H, INTTMmn output is generated. At
the same time, the value of the TDRmn register is
loaded to the TCRmn register, and the counter starts
counting down again.
At the slave channel 1, the values of the TDRmp
register are transferred to the TCRmp register,
triggered by INTTMmn of the master channel, and the
counter starts counting down. The output levels of
TOmp become active one count clock after generation
of the INTTMmn output from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
At the slave channel 2, the values of the TDRmq
register are transferred to TCRmq register, triggered
by INTTMmn of the master channel, and the counter
starts counting down. The output levels of TOmq
become active one count clock after generation of the
INTTMmn output from the master channel. It becomes
inactive when TCRmq = 0000H, and the counting
operation is stopped. After that, the above operation is
repeated.
Operation
stop
The TTmn (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically
return to 0 because they are trigger bits.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TCRmn, TCRmp, and TCRmq registers hold
count value and stop.
The TOmp and TOmq output are not initialized but
hold current status.
The TOEmp and TOEmq bits of slave channels are
cleared to 0 and value is set to the TOmp and TOmq
bits.
The TOmp and TOmq pins output the TOmp and
TOmq set levels.
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
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