RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 289 of 765
Mar 7, 2023
Figure 6-78. Operation Procedure When Multiple PWM Output Function Is Used (Output Two Types of PWMs) (3/3)
Software Operation Hardware Status
TAU stop To hold the TOmp and TOmq pin output levels
Clears the TOmp, TOmq bits to 0 after the value to
be held is set to the port register.
When holding the TOmp and TOmq pin output levels
are not necessary
Setting not required.
The TOmp and TOmq pin output levels are held by
port function.
The TAUmEN bit of the PER0 register is cleared
to 0.
Power-off status
All circuits are initialized and SFR of each channel
is also initialized.
(The TOmp and TOmq bits are cleared to 0 and
the TOmp and TOmq pins are set to port mode.)
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
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