RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 383 of 765
Mar 7, 2023
Figure 12-9. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0102H, F0103H (SSR01) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
0 0
Note 1
OVFm
n
FEFmn
Note 1
Framing error detection flag of channel n
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
●
1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
●
A stop bit is not detected when UART reception ends.
PEFmn Parity/ACK error detection flag of channel n
0 No error occurs.
1 Parity error occurs (during UART reception) or ACK is not detected (during I
2
C transmission).
<Clear condition>
●
1 is written to the PECTmn bit of the SIRmn register.
<Set conditions>
●
The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
●
No ACK signal is returned from the slave at the ACK reception timing during I
2
C transmission (ACK is not detected).
OVFmn Overrun error detection flag of channel n
0 No error occurs.
1 An error occurs
<Clear condition>
●
1 is written to the OVCTmn bit of the SIRmn register.
<Set conditions>
●
Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next receive
data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission/reception mode in each
communication mode).
●
Transmit data is not ready for slave transmission or transmission/reception in simplified SPI (CSI) mode.
Note 1. The SSR01 register only.
Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVFmn = 1) is detected.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1)
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