Renesas RL78/G15

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 415 of 765
Mar 7, 2023
(4) Processing flow (in continuous reception mode)
Figure 12-35. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Shift
register mn
SIp pin
SCKp
pin
Data receptionData reception
SSmn
STmn
SEmn
SDRmn
INTCSIp
TSFmn
Dummy data Dummy data Receive data 2
Receive data
1
Receive data 2 Receive data 3
BFFmn
MDmn0
<1>
<8>
<5>
<3> <
3> <4> <3> <6>
Receive data 1 Dummy data
Receive data 3
<4> <7>
Read Read Read
Reception & shift operation Reception & shift operation Reception & shift operation
<2> Write
<
2
>
Write <2> Write
Data reception
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remark 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-36 Flowchart of Master Reception (in
Continuous Reception Mode).
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01), mn = 00, 01