Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 471 of 765
Mar 7, 2023
(1) Register setting
Figure 12-76. Example of Contents of Registers for UART Reception of UART (UART0) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSm
n
CCSm
n
STSm
n
SISmn
0
MDmn
2
MDmn
1
MDmn
0
0/1 0 0 0 0 0 0 1 0 0/1 1 0 0 0 1 0
Operation clock (f
MCK
) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
0: Normal reception
1: Reverse reception
Operation mode of channel n
0: Transfer end interrupt
(b) Serial mode register mr (SMRmr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmr
CKSmr
CCSm
r
MDmr
2
MDmr
1
MDmr
0
0/1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Same setting value as CKSmn bit Operation mode of channel r
0: Transfer end interrupt
(c) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEm
n
RXEm
n
DAPm
n
CKPm
n
EOCm
n
PTCm
n1
PTCm
n0
DIRmn
SLCm
n1
SLCm
n0
DLSmn
1
DLSmn
0
0 1 0 0 0 0/1 0/1 0/1 0/1 0 0 1 0 1 0/1 0/1
Setting of parity bit
00B: No parity check
01B: No parity judgment
10B: Even parity check
11B: Odd parity check
Selection of data transfer sequence
0: Inputs data with MSB first
1: Inputs data with LSB first
Setting of data length
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
Receive data register
0
Note 1
RXDq
(Note 1, Caution, and Remarks are listed on the next page.)

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English