RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 486 of 765
Mar 7, 2023
(1) Register setting
Figure 12-85. Example of Contents of Registers for Address Field Transmission of Simplified I
2
C (IIC00, IIC01) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSm
n
CCSm
n
STSm
n
Note 1
SISmn
0
Note 1
MDmn
2
MDmn
1
MDmn
0
0/1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
Operation clock (f
MCK
) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Operation mode of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEm
n
RXEm
n
DAPm
n
CKPm
n
EOCm
n
PTCm
n1
PTCm
n0
DIRmn
SLCm
n1
Note 2
SLCm
n0
DLSm
n1
DLSm
n0
1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit
(ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
Transmit data setting (address + R/W)
0
SIOr
(d) Serial output register m (SOm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
CKOm
1
CKOm
0
SOm1
SOm0
0 0 0 0 0 0 0/1 0/1 0 0 0 0 0 0 0/1 0/1
Start condition is generated by manipulating the SOmn bit.
(e) Serial output enable register m (SOEm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
SOEm
1
SOEm
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1
SOEmn = 0 until the start condition is generated, and SOEmn = 1 after generation.
(Note 1, Note 2, and Remarks are listed on the next page.)
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