RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 509 of 765
Mar 7, 2023
(1) IICA shift register 0 (IICA0)
The IICA0 register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the
serial clock. The IICA0 register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing to and reading from the IICA0 register.
Writing to the IICA0 register during the clock stretch period releases clock stretching and starts data transfer.
The IICA0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-3. Format of IICA Shift Register 0 (IICA0)
Address: FFF50H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
IICA0
Caution 1. Do not write data to the IICA0 register during data transfer.
Caution 2. Write to or read from the IICA0 register only during the clock stretch period. Access to the IICA0
register in the communication state other than during the clock stretch period is prohibited. When
the device serves as the master, however, the IICA0 register can be written only once after the
communication trigger bit (STT0) is set to 1.
Caution 3. When communication is reserved, write data to the IICA0 register after the interrupt triggered by a
stop condition is detected.
(2) Slave address register 0 (SVA0)
This register holds seven bits (A6, A5, A4, A3, A2, A1, and A0) of the local address when in slave mode.
The SVA0 register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (the start condition is detected).
Reset signal generation clears this register to 00H.
Figure 13-4. Format of Slave Address Register 0 (SVA0)
Address: F0234H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
SVA0 A6 A5 A4 A3 A2 A1 A0 0
Note 1
Note 1. Be sure to clear bit 0 to 0.
To Next Page
Loading...
Need help?
General
