RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 510 of 765
Mar 7, 2023
(3) SO latch
The SO latch is used to retain the output level of the SDAA0 pin.
(4) Wakeup controller
This circuit generates an interrupt request (INTIICA0) when the received address matches the address value set in slave
address register 0 (SVA0) or when an extension code is received.
(5) Serial clock counter
This counter counts the serial clock cycles that are output or input during transmit/receive operations and is used to verify
that 8-bit data has been transmitted or received.
(6) Interrupt request signal generator
This circuit controls the generation of an interrupt request signal (INTIICA0).
An I
2
C interrupt request is generated by the following two triggers.
●
Falling edge of 8th or 9th clock of the serial clock (set by the WTIM0 bit)
●
Interrupt request generated when a stop condition is detected (set by the SPIE0 bit)
Remark WTIM0 bit: Bit 3 of IICA control register 00 (IICCTL00)
SPIE0 bit: Bit 4 of IICA control register 00 (IICCTL00)
(7) Serial clock controller
In master mode, this circuit generates the clock for output to the SCLA0 pin from a sampling clock.
(8) Clock stretch controller
This circuit controls the timing of clock stretching.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each state.
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