RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 511 of 765
Mar 7, 2023
(10) Data hold time correction circuit
This circuit generates the hold time for data after the falling edge of the serial clock.
(11) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, while communication reservation is disabled (IICRSV0 bit = 1) and the bus is not released (IICBSY0 bit = 1),
start condition requests are ignored and the STCF0 bit is set to 1.
(12) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
(13) Bus state detector
This circuit detects whether or not the bus is released by detecting a start condition or stop condition.
However, as the bus state cannot be detected immediately after the operation, use the STCEN0 bit to set the initial state
of this circuit.
Remark STT0 bit: Bit 1 of IICA control register 00 (IICCTL00)
SPT0 bit: Bit 0 of IICA control register 00 (IICCTL00)
IICRSV0 bit: Bit 0 of IICA flag register 0 (IICF0)
IICBSY0 bit: Bit 6 of IICA flag register 0 (IICF0)
STCF0 bit: Bit 7 of IICA flag register 0 (IICF0)
STCEN0 bit: Bit 1 of IICA flag register 0 (IICF0)
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