RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 544 of 765
Mar 7, 2023
Table 13-4. State when Arbitration Occurred and Interrupt Request Generation Timing
State when Arbitration Occurred Interrupt Request Generation Timing
During address transmission Falling edge of 8th or 9th clock following byte transfer
Note 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
Restart condition is detected during data transfer
Stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1)
Note 2
Data is at low level while attempting to generate a restart condition Falling edge of 8th or 9th clock following byte transfer
Note 1
Stop condition is detected while attempting to generate restart condition When stop condition is generated (when SPIE0 = 1)
Note 2
Data is at low level while attempting to generate a stop condition Falling edge of 8th or 9th clock following byte transfer
Note 1
When SCLA0 is at low level while attempting to generate a restart
condition
Note 1. When the WTIM0 bit (bit 3 of IICA control register 00 (IICCTL00)) = 1, an interrupt request occurs at the
falling edge of the 9th clock. When WTIM0 = 0, the extension code's slave address is received, an interrupt
request occurs at the falling edge of the 8th clock.
Note 2. If there is a possibility that arbitration will occur, set SPIE0 = 1 for master operation.
Remark SPIE0: Bit 4 of IICA control register 00 (IICCTL00)
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