Renesas RL78/G15 - Page 549

RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 549 of 765
Mar 7, 2023
Figure 13-24 shows the communication reservation timing.
Figure 13-24. Communication Reservation Timing
21 3 4 5 6 21 3 4 5 67 8 9
SCLA0
SDAA0
Program processing
Hardware processing
STT0 = 1
Generated by the master
with bus mastership
Write to
IICA0
Communi-
cation
reservation
Set
STD0
Set SPD0
and
INTIICA0
Remark IICA0: IICA shift register 0
STT0: Bit 1 of IICA control register 00 (IICCTL00)
STD0: Bit 1 of IICA status register 0 (IICS0)
SPD0: Bit 0 of IICA status register 0 (IICS0)
Communication reservations are accepted at the timing shown in Figure 13-25. After bit 1 (STD0) of IICA status register
0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IICA control register 00
(IICCTL00) to 1 before a stop condition is detected.
Figure 13-25. Timing for Accepting Communication Reservations
SCLA0
SDAA0
STD0
SPD0
Standby mode (communication can be reserved by setting STT0 to 1 during this period)