Renesas RL78/G15 - Page 550

RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 550 of 765
Mar 7, 2023
Figure 13-26 shows the procedure for communication reservation.
Figure 13-26. Communication Reservation Procedure
Yes
No
Set the STT0 flag
(communication reservation
)
DI
SET1 STT0
Define communication
reservation
Wait
MSTS
0 = 0
?
Cancel communication
reservation
MOV IICA0
, #××H
EI
(Communication
reservation)
Note
2
(Start condition generation)
Define that communication reservation is
in effect (define and set the user flag in
the desired RAM
)
Secure a wait time
Note
1
by software
Confirmation of communication reservation
Clear the user flag
IICA0 write operation
Note 1. A wait time is as follows.
(IICWL0 setting value + IICWH0 setting value + 4)/f
CLK
+ t
F
× 2
Note 2. In communication reservation operation, writing to IICA shift register 0 (IICA0) is executed in response to a
stop condition interrupt request.
Remark STT0: Bit 1 of IICA control register 00 (IICCTL00)
MSTS0: Bit 7 of IICA status register 0 (IICS0)
IICA0: IICA shift register 0
IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F
: SDAA0 and SCLA0 signal falling time
f
CLK
: CPU/peripheral hardware clock frequency