Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 559 of 765
Mar 7, 2023
Figure 13-28. Master Operation in Multi-master System (3/3)
Write to IICA0
MSTS0 = 1?
WTIM0 = 1
STT0 = 1
EXC0 = 1 or COI0 = 1?
Restart?
No
Wait for detection of ACK
Yes
Yes
WREL0 = 1
ACKE0 = 0
WTIM0 = 1
End of transfer?
Read IICA0
INTIICA0 interrupt
occurred?
No
Wait for detection of ACK
Communication
processing
Communication processing
C
INTIICA0 interrupt
occurred?
2
ACKD0 = 1?
Yes
TRC0 = 1?
Yes
Yes
Write to IICA0
INTIICA0 interrupt
occurred?
No
Wait for data transmission
Start transmission
MSTS0 = 1?
ACKD0 = 1?
End of transfer?
Yes
Yes
Yes
No
C
2
Slave operation
Yes
END
SPT0 = 1
MSTS0 = 1?
INTIICA0 interrupt
occurred?
2
MSTS0 = 1?
No
Wait for data reception
WREL0 = 1
2
ACKE0 = 1
WTIM0 = 0
Start reception
No
No
Yes
Yes
Yes
Yes
Yes
No
1
Non-participation in
communications
No
No
2
No
No
No
No
Start communication
(specify the address and transfer direction)
Yes
Remark 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
Remark 2. To use the device as a master in the multi-master system, read the MSTS0 bit to check the arbitration
result each time interrupt INTIICA0 is generated.
Remark 3. To use the device as a slave in the multi-master system, check the status by reading IICA status register 0
(IICS0) and IICA flag register 0 (IICF0) each time interrupt INTIICA0 is generated, and determine next
processing to be performed.

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English