Renesas RL78/G15

RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 588 of 765
Mar 7, 2023
Figure 13-31. Example of Master to Slave Communications
(9th Cycle Clock Stretching is Selected for Both Master and Slave) (2/4)
(2) Address ~ data ~ data
IICA
0
ACKD0
(ACK detection)
<5
> <9>
L
H
H
D
1
6 D
1
5
Note
1
Master side
STT
0
(ST trigger
)
SPT
0
(SP trigger)
WREL0
(release clock stretching
)
INTIICA0
(interrupt
)
TRC0
(
transmission/
reception)
Bus line
SCLA0 (bus)
(
clock line)
SDAA0 (bus)
(data line
)
D
1
7 D
1
4 D
1
3 D
1
2 D
1
1 D
2
7
Slave side
IICA0
ACKD
0
(ACK detection)
<7>
<8>
H
H
L
L
<10
>
Note
2
STD0
(ST detection)
SPD0
(
SP detection)
WTIM
0
(Clock stretch timing control
)
ACKE0
(ACK control)
MSTS0
(communication state)
WREL0
(release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
WTIM0
(
Clock stretch timing control
)
ACKE0
(ACK control
)
MSTS
0
(communication state)
D
1
0
Note 1
H
L
H
<4>
<3>
L
Note 2
<6>
L
ACK
W ACK
: Clock stretching by the slave
: Clock stretching by the master and slave
Note 1. To release clock stretching in transmission by the master, write data to the IICA0 register instead of setting
the WREL0 bit.
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