RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 587 of 765
Mar 7, 2023
Note 2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is at
least 4.0 μs when standard mode is set and at least 0.6 μs when fast mode is set.
Note 3. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit.
Explanation of <1> to <6> in Figure 13-31 (1) Start condition ~ address ~ data is given below.
<1> When the start condition trigger is set by the master (STT0 = 1), the bus data line (SDAA0) goes low and a start
condition (SDAA0 = 0, SCLA0 = 1) is generated. After that, when the start condition is detected, the master
enters the master communication state (MSTS0 = 1). It is ready for communications when the bus clock line
goes low (SCLA0 = 0) after the hold time has elapsed.
<2> When the master writes the address + W (transmission) to IICA shift register 0 (IICA0), the slave address is
transmitted.
<3> In the slave, if the address received matches its local address (SVA0 value)
Note 1
, an ACK is sent to the master
by the hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master issues an interrupt (INTIICA0: address transmission end interrupt) at the falling edge of the 9th
clock. The slave with the matching address applies clock stretching (SCLA0 = 0) and issues an interrupt
(INTIICA0: address match interrupt)
Note 1
.
<5> The master writes transmit data to the IICA0 register and releases clock stretching by the master.
<6> If the slave releases clock stretching (WREL0 = 1), the master starts to transfer data to the slave.
Note 1. If the transmitted address does not match the address of the slave, the slave does not return an ACK to the
master (NACK: SDAA0 = 1). The slave also neither issue the INTIICA0 interrupt (address match interrupt) nor
apply clock stretching.
The master, however, issues the INTIICA0 interrupt (address transmission end interrupt) in response to an
ACK or NACK.
Remark <1> to <15> in Figure 13-31 represent a series of operation procedures for data communications via the I
2
C
bus.
Figure 13-31 (1) Start condition ~ address ~ data shows steps <1> to <6>.
Figure 13-31 (2) Address ~ data ~ data shows steps <3> to <10>.
Figure 13-31 (3) Data ~ data ~ stop condition shows steps <7> to <15>.
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