RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 589 of 765
Mar 7, 2023
Note 2. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit.
Explanation of <3> to <10> in Figure 13-31 (2) Address ~ data ~ data is given below.
<3> In the slave, if the address received matches its local address (SVA0 value)
Note 1
, an ACK is sent to the master
by the hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master issues an interrupt (INTIICA0: address transmission end interrupt) at the falling edge of the 9th
clock. The slave with the matching address applies clock stretching (SCLA0 = 0) and issues an interrupt
(INTIICA0: address match interrupt)
Note 1
.
<5> The master writes transmit data to the IICA shift register 0 (IICA0) and releases clock stretching by the master.
<6> If the slave releases clock stretching (WREL0 = 1), the master starts to transfer data to the slave.
<7> After data transfer is completed, because ACKE0 = 1 for the slave, an ACK is sent to the master by the
hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<8> The master and slave apply clock stretching (SCLA0 = 0) at the falling edge of the 9th clock, and both the
master and slave issue an interrupt (INTIICA0: transfer end interrupt).
<9> The master writes transmit data to the IICA0 register and releases clock stretching by the master.
<10> When the slave reads the received data and releases clock stretching (WREL0 = 1), the master starts to
transmit data to the slave.
Note 1. If the transmitted address does not match the address of the slave, the slave does not return an ACK to the
master (NACK: SDAA0 = 1). The slave also neither issue the INTIICA0 interrupt (address match interrupt) nor
apply clock stretching.
The master, however, issues the INTIICA0 interrupt (address transmission end interrupt) in response to an
ACK or NACK.
Remark <1> to <15> in Figure 13-31 represent a series of operation procedures for data communications via the I
2
C
bus.
Figure 13-31 (1) Start condition ~ address ~ data shows steps <1> to <6>.
Figure 13-31 (2) Address ~ data ~ data shows steps <3> to <10>.
Figure 13-31 (3) Data ~ data ~ stop condition shows steps <7> to <15>.
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