RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 598 of 765
Mar 7, 2023
Figure 13-32. Example of Slave to Master Communications
(8th Cycle Clock Stretching is Changed to 9th Cycle Clock Stretching for Master,
9th Cycle Clock Stretching is Selected for Slave) (3/3)
(3) Data ~ data ~ stop condition
IICA
0
ACKD0
(ACK detection)
D
16
6 D
16
5
Master side
STT0
(ST trigger)
SPT0
(SP trigger)
WREL0
(release clock stretching)
INTIICA0
(interrupt
)
TRC0
(transmission
/reception)
Bus line
SCLA
0 (bus)
(clock line)
SDAA0 (bus)
(data line)
D
16
4 D
16
3 D
16
2 D
16
1
Slave side
IICA
0
ACKD0
(ACK detection)
H
H
L
STD0
(ST detection)
SPD0
(SP detection)
WTIM0
(Clock stretch timing control)
ACKE0
(ACK control)
MSTS0
(
communication state)
WREL0
(
release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
WTIM0
(Clock stretch timing control)
ACKE0
(ACK control)
MSTS0
(communication state)
D
16
0
<8>
<10
>
L
D
15
0
<19>
Stop condition
ACK NACK
L
L
<9>
Note 4
<11>
<12>
Note 3
D
16
7
Note 1
<13>
Note 1
<14
>
<15
>
<17>
Note 1,
Note 4
: Clock stretching by the master
: Clock stretching by the slave
: Clock stretching by the master and slave
Note 2
<18>
Note 1. To release clock stretching, write FFH to IICA0 or set the WREL0 bit.
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