RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 599 of 765
Mar 7, 2023
Note 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition
after a stop condition has been issued is at least 4.0 μs when standard mode is set and at least 0.6 μs when
fast mode is set.
Note 3. To release clock stretching in transmission by the slave, write data to the IICA0 register instead of setting the
WREL0 bit.
Note 4. If clock stretching in transmission by the slave is released by setting the WREL0 bit, the TRC0 bit will be
cleared.
Explanation of <8> to <19> in Figure 13-32 (3) Data ~ data ~ stop condition is given below.
<8> The master applies clock stretching (SCLA0 = 0) at the falling edge of the 8th clock and issues an interrupt
(INTIICA0: transfer end interrupt). Because ACKE0 = 0 for the master, an ACK is sent to the slave by the
hardware.
<9> The master reads the received data and releases clock stretching (WREL0 = 1).
<10> The ACK is detected by the slave (ACKD0 = 1) at the rising edge of the 9th clock.
<11> The slave applies clock stretching (SCLA0 = 0) at the falling edge of the 9th clock and issues an interrupt
(INTIICA0: transfer end interrupt).
<12> When the slave writes transmit data to the IICA0 register, clock switching by the slave is released. The slave
then starts to transfer data to the master.
<13> The master issues an interrupt (INTIICA0: transfer end interrupt) at the falling edge of the 8th clock and applies
clock stretching (SCLA0 = 0). Because ACK control (ACKE0 = 1) is used, the bus data line is at the low level
(SDAA0 = 0) at this stage.
<14> The master sets NACK as the response (ACKE0 = 0) and changes the timing of clock stretching to the 9th clock
(WTIM0 = 1).
<15> If the master releases clock stretching (WREL0 = 1), the slave detects the NACK (ACK = 0) at the rising edge of
the 9th clock.
<16> The master and slave apply clock stretching (SCLA0 = 0) at the falling edge of the 9th clock, and both the
master and slave issue an interrupt (INTIICA0: transfer end interrupt).
<17> When the master issues a stop condition (SPT0 = 1), the bus data line is cleared (SDAA0 = 0) and the master
releases clock stretching. The master then waits until the bus clock line is set (SCLA0 = 1).
<18> The slave acknowledges the NACK, halts transmission, and releases clock stretching (WREL0 = 1) to end
communications. Once the slave releases clock stretching, the bus clock line is set (SCLA0 = 1).
<19> When the master confirms that the bus clock line has been set (SCLA0 = 1), it sets the bus data line (SDAA0 =
1) and issues a stop condition (SDAA0 changes from 0 to 1 with SCLA0 =1) after the stop condition setup time
has elapsed. The slave detects this stop condition and issues an interrupt (INTIICA0: stop condition interrupt).
Remark <1> to <19> in Figure 13-32 represent a series of operation procedures for data communications via the I
2
C
bus.
Figure 13-32 (1) Start condition ~ address ~ data shows steps <1> to <7>.
Figure 13-32 (2) Address ~ data ~ data shows steps <3> to <12>.
Figure 13-32 (3) Data ~ data ~ stop condition shows steps <8> to <19>.
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