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Renesas RL78/G15 - Page 61

Renesas RL78/G15
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RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 61 of 765
Mar 7, 2023
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the
subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. For details, see CHAPTER 18 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH can be used as an on-chip debug security ID setting area. For details, see
CHAPTER 20 ON-CHIP DEBUG FUNCTION.

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