RL78/G15 CHAPTER 15 STANDBY FUNCTION
R01UH0959EJ0110 Rev.1.10 Page 626 of 765
Mar 7, 2023
Table 15-1. Operating Status in HALT Mode
HALT Mode Setting
Item
When HALT Instruction is Executed While CPU is Operating on Main System Clock
When CPU is Operating on
High-speed On-chip Oscillator
Clock (f
IH
)
When CPU is Operating on
X1 Clock (f
X
)
When CPU is Operating on
External Main System Clock
(f
EX
)
System clock Clock supply to the CPU is stopped
Main system clock f
IH
Operation continues
(cannot be stopped)
Operation disabled
f
X
Operation disabled
Operation continues
(cannot be stopped)
Cannot operate
f
EX
Cannot operate
Operation continues
(cannot be stopped)
f
IL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and bit 4 (WUTMMCK0) of
operation speed mode control register (OSMC)
●
WUTMMCK0 = 1: Oscillates
●
WUTMMCK0 = 0 and WDTON = 0: Stops
●
WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
●
WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Illegal-memory access detection
function
Port (latch) Status before HALT mode was set is retained
Timer array unit Operable
12-bit interval timer
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
WDSTBYON = 0: Operation stopped
WDSTBYON = 1: Operation continues
Clock output/buzzer output Operable
A/D converter
Comparator
Serial array unit (SAU)
Serial interface (IICA)
Selectable power-on-reset
function
External interrupt
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH
: High-speed on-chip oscillator clock
f
IL
: Low-speed on-chip oscillator clock
f
X
: X1 clock
Note 1
f
EX
: External main system clock
Note 1
Note 1. 16-pin and 20-pin products only.
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