Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 24 ELECTRICAL SPECIFICATIONS (T
A
= −40 to +105°C, TA = −40 to +125°C)
R01UH0959EJ0110 Rev.1.10 Page 744 of 765
Mar 7, 2023
(4) Simplified I
2
C mode
[T
A
= −40 to +105°C: G products, T
A
= −40 to +125°C: M products, 2.4 V ≤ V
DD
≤ 5.5 V, V
SS
= 0 V]
Item Symbol Condition MIN. MAX. Unit
SCLr clock frequency f
SCL
2.7 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
400
Note 1
kHz
2.4 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
100
Note 1
kHz
Hold time when SCLr = “L” t
LOW
2.7 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
1200 ns
2.4 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
4600 ns
Hold time when SCLr = “H” t
HIGH
2.7 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
1200 ns
2.4 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
4600 ns
Data setup time (reception) t
SU:DAT
2.7 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
1/f
MCK
+ 220
Note 2
ns
2.4 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
1/f
MCK
+ 580
Note 2
ns
Data hold time (transmission) t
HD:DAT
2.7 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
0 770 ns
2.4 V ≤ V
DD
≤ 5.5 V
C
b
= 100 pF, R
b
= 3 kΩ
0 1420 ns
Note 1. The value must also be no greater than f
MCK
/4.
Note 2. Set f
MCK
so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.
Caution Select the N-ch open drain output (V
DD
tolerance) mode for the SDAr pin by using port output mode
register 0, 2, or 4 (POM0, 2, or 4).
Simplified I
2
C mode connection diagram
RL78
microcontroller
User device
SDAr
SCLr
SDA
SCL
V
DD
R
b

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English