5–40 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Cyclone IV Device Handbook, October 2012 Altera Corporation
Volume 1
Tab le 5 –1 3 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECT
setting.
To perform one dynamic phase-shift, follow these steps:
1. Set
PHASEUPDOWN
and
PHASECOUNTERSELECT
as required.
2. Assert
PHASESTEP
for at least two
SCANCLK
cycles. Each
PHASESTEP
pulse allows one
phase shift.
3. Deassert
PHASESTEP
after
PHASEDONE
goes low.
4. Wait for
PHASEDONE
to go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple phase-
shifts.
PHASEUPDOWN
and
PHASECOUNTERSELECT
signals are synchronous to
SCANCLK
and must
meet the t
su
and t
h
requirements with respect to the
SCANCLK
edges.
1 You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180, in other words, a phase shift of 5 ns.
scanclk
Free running clock from core used in
combination with
phasestep
to enable or
disable dynamic phase shifting. Shared with
scanclk
for dynamic reconfiguration.
GCLK or I/O pins
PLL
reconfiguration
circuit
phasedone
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
De
-asserts on the rising edge of
scanclk
.
PLL reconfiguration
circuit
Logic array or
I/O pins
Table 5–12. Dynamic Phase Shifting Control Signals (Part 2 of 2)
Signal Name Description Source Destination
Table 5–13. Phase Counter Select Mapping
phasecounterselect
Selects
[2] [1] [0]
0 0 0 All Output Counters
0 0 1 M Counter
010 C0 Counter
011 C1 Counter
100 C2 Counter
101 C3 Counter
110 C4 Counter
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