Altera Cyclone IV - Page 333

Chapter 1: Cyclone IV Transceivers Architecture 1–53
Transceiver Functional Modes
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
Configuring the hard IP module requires using the PCI Express Compiler. When
configuring the transceiver for PCIe implementation with hard IP module, the byte
serializer and deserializer are not enabled, providing an 8-bit transceiver-PIPE-hard
IP data interface width running at 250 MHz clock frequency.
f For more information about PCIe implementation with hard IP module, refer to the
PCI Express Compiler User Guide.
Figure 1–49 shows the transceiver configuration in PIPE mode.
1 When configuring the transceiver into PIPE mode using ALTGX megafunction for
PCIe implementation, the PHY-MAC, data link and transaction layers must be
implemented in user logics. The PCIe hard IP block is bypassed in this configuration.
Figure 1–49. Transceiver Configuration in PIPE Mode
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
2.5
Disabled
Automatic Synchronization
State Machine (10-Bit)
16-Bit
PCI Express (PIPE)
×1, ×2, ×4
Disabled
Enabled
Enabled
Enabled
Data Rate (Gbps)
125