Altera Cyclone IV - Page 349

Chapter 1: Cyclone IV Transceivers Architecture 1–69
Transceiver Functional Modes
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
Figure 1–63 shows the transceiver channel datapath and clocking when configured in
XAUI mode.
Figure 1–63. Transceiver Channel Datapath and Clocking when Configured in XAUI Mode
Notes to Figure 1–63:
(1) Channel 1 low-speed recovered clock.
(2) Low-speed recovered clock.
(3) High-speed recovered clock.
(2)(1)
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS 3 Transmitter Channel PMA 3
Serializer
PCIe Hard IP
FPGA
Fabric
PIPE Interface
Tx Phase
Comp
FIFO
tx_dataout[3]
wr_clk rd_clk wr_clk rd_clk
high-speed
clock
low-speed clock
rx_coreclk[3] tx_coreclk[3]
Receiver Channel PCS 3 Receiver Channel PMA 3
rx_datain[3]
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
(3)
Word
Aligner
Rx
Phase
Comp
FIFO
/2
/2
(2)(1)
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS 2 Transmitter Channel PMA 2
Serializer
Tx Phase
Comp
FIFO
tx_dataout[2]
wr_clk rd_clk wr_clk rd_clk
high-speed
clock
rx_coreclk[2] tx_coreclk[2]
Receiver Channel PCS 2 Receiver Channel PMA 2
rx_datain[2]
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
(3)
Word
Aligner
Rx
Phase
Comp
FIFO
/2
(2)(1)
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS 1 Transmitter Channel PMA 1
Serializer
Tx Phase
Comp
FIFO
tx_dataout[1]
wr_clk rd_clk wr_clk rd_clk
high-speed
clock
rx_coreclk[1] tx_coreclk[1]
Receiver Channel PCS 1 Receiver Channel PMA 1
rx_datain[1]
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
(3)
Word
Aligner
Rx
Phase
Comp
FIFO
/2
(2)(1)
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS 0 Transmitter Channel PMA 0
Serializer
Tx Phase
Comp
FIFO
tx_dataout[0]
wr_clk rd_clk wr_clk rd_clk
high-speed
clock
rx_coreclk[0] tx_coreclk[0]
Receiver Channel PCS 0 Receiver Channel PMA 0
rx_datain[0]
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
(3)
Word
Aligner
Rx
Phase
Comp
FIFO
/2
/2
/2
/2
coreclkout
/2