Altera Cyclone IV - Page 354

1–74 Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Cyclone IV Device Handbook, February 2015 Altera Corporation
Volume 2
Figure 1–66 shows the transceiver channel datapath and clocking when configured in
deterministic latency mode.
Figure 1–66. Transceiver Channel Datapath and Clocking when Configured in Deterministic Latency Mode
Note to Figure 1–66:
(1) High-speed recovered clock.
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS Transmitter Channel PMA
Serializer
PCIe Hard IP
FPGA
Fabric
PIPE Interface
Tx Phase
Comp
FIFO
tx_datain
tx_dataout
wr_clk rd_clk
wr_clk rd_clk
high-speed
clock
low-speed clock
low-speed recovered clock
tx_clkout
rx_clkout
Receiver Channel PCS Receiver Channel PMA
rx_dataout
rx_datain
Deserial-
izer
CDR
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
(1)
Word
Aligner
Rx
Phase
Comp
FIFO
/2
/2
Byte
De-
serializer