NXP Semiconductors MC9S12G - Page 226

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
228 NXP Semiconductors
2.4.3.45 Port J Pull Device Enable Register (PERJ)
Table 2-70. DDRJ Register Field Descriptions
Field Description
7-0
DDRJ
Port J data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x026C (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0
W
Reset11111111
Address 0x026C (G3) Access: User read/write
1
76543210
R0000
PERJ3 PERJ2 PERJ1 PERJ0
W
Reset00001111
Figure 2-45. Port J Pull Device Enable Register (PERJ)
Table 2-71. PERJ Register Field Descriptions
Field Description
7-0
PERJ
Port J pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled