NXP Semiconductors MC9S12G - Page 225

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 227
2.4.3.43 Port J Input Register (PTIJ)
2.4.3.44 Port J Data Direction Register (DDRJ)
Address 0x0269 (G1, G2) Access: User read only
1
1
Read: Anytime
Write:Never
76543210
R PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0
W
Reset00000000
Address 0x0269 (G3) Access: User read only
1
76543210
R 0 0 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0
W
Reset00000000
Figure 2-43. Port J Input Register (PTIJ)
Table 2-69. PTIJ Register Field Descriptions
Field Description
7-0
PTIJ
Port J input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x026A (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0
W
Reset00000000
Address 0x026A (G3) Access: User read/write
1
76543210
R0000
DDRJ3 DDRJ2 DDRJ1 DDRJ0
W
Reset00000000
Figure 2-44. Port J Data Direction Register (DDRJ)