NXP Semiconductors MC9S12G User Manual

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 231
2.4.3.49 Port AD Data Register (PT0AD)
2.4.3.50 Port AD Data Register (PT1AD)
Address 0x0270 (G1, G2) Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0
W
Reset00000000
Address 0x0270 (G3) Access: User read/write
1
76543210
R0000
PT0AD3 PT0AD2 PT0AD1 PT0AD0
W
Reset00000000
Figure 2-49. Port AD Data Register (PT0AD)
Table 2-75. PT0AD Register Field Descriptions
Field Description
7-0
PT0AD
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose
output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”).
Address 0x0271 Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
76543210
R
PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
W
Reset00000000
Figure 2-50. Port AD Data Register (PT1AD)

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English