Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
232 NXP Semiconductors
2.4.3.51 Port AD Input Register (PTI0AD)
2.4.3.52 Port AD Input Register (PTI1AD)
Table 2-76. PT1AD Register Field Descriptions
Field Description
7-0
PT1AD
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose
output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”).
Address 0x0272 (G1, G2) Access: User read only
1
1
Read: Anytime
Write: Never
76543210
R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0
W
Reset00000000
Address 0x0272 (G3) Access: User read only
1
76543210
R 0 0 0 0 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0
W
Reset00000000
Figure 2-51. Port AD Input Register (PTI0AD)
Table 2-77. PTI0AD Register Field Descriptions
Field Description
7-0
PTI0AD
Port AD input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0273 Access: User read only
1
1
Read: Anytime
Write: Never
76543210
R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0
W
Reset00000000
Figure 2-52. Port AD Input Register (PTI1AD)
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