NXP Semiconductors MC9S12G User Manual

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
236 NXP Semiconductors
2.4.3.58 Port AD Pull Enable Register (PER1AD)
2.4.3.59 Port AD Polarity Select Register (PPS0AD)
Address 0x0279 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
W
Reset00000000
Figure 2-57. Port AD Pullup Enable Register (PER1AD)
Table 2-84. PER1AD Register Field Descriptions
Field Description
7-0
PER1AD
Port AD pull enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x027A (G1, G2) Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0
W
Reset00000000
Address 0x027A (G3) Access: User read/write
1
76543210
R0000
PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0
W
Reset00000000
Figure 2-58. Port AD Polarity Select Register (PPS0AD)

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English