S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
372 NXP Semiconductors
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table 10-9. CPMURTI Field Descriptions
Field Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 10-10
1 Decimal based divider value. See Table 10-11
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Table 10-10 and Table 10-11.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 10-10 and Table 10-11 show all possible divide values selectable by the
CPMURTI register.
Table 10-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[3:0]
RTR[6:4] =
000
(OFF)
001
(2
10
)
010
(2
11
)
011
(2
12
)
100
(2
13
)
101
(2
14
)
110
(2
15
)
111
(2
16
)
0000 (1)
OFF
1
2
10
2
11
2
12
2
13
2
14
2
15
2
16
0001 (2)
OFF 2x2
10
2x2
11
2x2
12
2x2
13
2x2
14
2x2
15
2x2
16
0010 (3)
OFF 3x2
10
3x2
11
3x2
12
3x2
13
3x2
14
3x2
15
3x2
16
0011 (4)
OFF 4x2
10
4x2
11
4x2
12
4x2
13
4x2
14
4x2
15
4x2
16
0100 (5)
OFF 5x2
10
5x2
11
5x2
12
5x2
13
5x2
14
5x2
15
5x2
16
0101 (6)
OFF 6x2
10
6x2
11
6x2
12
6x2
13
6x2
14
6x2
15
6x2
16
0110 (7)
OFF 7x2
10
7x2
11
7x2
12
7x2
13
7x2
14
7x2
15
7x2
16
0111 (8)
OFF 8x2
10
8x2
11
8x2
12
8x2
13
8x2
14
8x2
15
8x2
16
1000 (9)
OFF 9x2
10
9x2
11
9x2
12
9x2
13
9x2
14
9x2
15
9x2
16
1001 (10)
OFF 10x2
10
10x2
11
10x2
12
10x2
13
10x2
14
10x2
15
10x2
16
1010 (11)
OFF 11x2
10
11x2
11
11x2
12
11x2
13
11x2
14
11x2
15
11x2
16
1011 (12)
OFF 12x2
10
12x2
11
12x2
12
12x2
13
12x2
14
12x2
15
12x2
16
1100 (13)
OFF 13x2
10
13x2
11
13x2
12
13x2
13
13x2
14
13x2
15
13x2
16
1101 (14)
OFF 14x2
10
14x2
11
14x2
12
14x2
13
14x2
14
14x2
15
14x2
16
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