Timer Module (TIM16B6CV3)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 725
22.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)
Read: Anytime
Write: Anytime
Table 22-4. TSCR1 Field Descriptions
Field Description
7
TEN
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is
generated by the timer prescaler.
6
TSWAI
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
out of wait.
TSWAI also affects pulse accumulator.
5
TSFRZ
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a
separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
3
PRNT
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
Module Base + 0x0007
76543210
R
RESERVED RESERVED TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
W
Reset00000000
Figure 22-9. Timer Toggle On Overflow Register 1 (TTOV)
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