NXP Semiconductors MC9S12G - Page 748

Timer Module (TIM16B8CV3)
MC9S12G Family Reference Manual Rev.1.27
750 NXP Semiconductors
Write: Anytime.
23.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 23-11. TCTL3/TCTL4 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field Description
7:0
EDGnB
EDGnA
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 23-12. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
Module Base + 0x000C
76543210
R
C7I C6I C5I C4I C3I C2I C1I C0I
W
Reset00000000
Figure 23-18. Timer Interrupt Enable Register (TIE)
Table 23-13. TIE Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.