Timer Module (TIM16B8CV3)
MC9S12G Family Reference Manual Rev.1.27
754 NXP Semiconductors
23.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
Read: Any time
Write: Any time
When PAEN is set, the Pulse Accumulator counter is enabled. The Pulse Accumulator counter shares the
input pin with IOC7.
Module Base + 0x0020
76543210
R0
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
W
Reset00000000
Unimplemented or Reserved
Figure 23-24. 16-Bit Pulse Accumulator Control Register (PACTL)
Table 23-18. PACTL Field Descriptions
Field Description
6
PAEN
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
5
PAMOD
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 23-19.
0 Event counter mode.
1 Gated time accumulation mode.
4
PEDGE
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See Table 23-19.
0 Falling edges on IOC7 pin cause the count to be increased.
1 Rising edges on IOC7 pin cause the count to be increased.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (Bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (Bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
3:2
CLK[1:0]
Clock Select Bits — Refer to Table 23-20.
1
PAOVI
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
0
PAI
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
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