RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 209 of 765
Mar 7, 2023
(2) Operation of event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the TImn
input.
Figure 6-25. Operation Timing (In Event Counter Mode)
f
MCK
TSmn (Write)
TEmn
Start trigger
detection signal
TCRmn
TDRmn
m
<1>
<2>
Edge detection Edge detection
<4>
<1>
<3>
<3>
Initial
value
m m – 1 m – 2
TImn input
Count clock
Remark Figure 6-25 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge
detection becomes 2 f
MCK
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The
error per one period occurs be the asynchronous between the period of the TImn input and that of the count
clock (f
MCK
).
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