RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 219 of 765
Mar 7, 2023
(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When timer output level register m (TOLm) setting has been changed during timer operation
When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation
timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output level of the TOmn pin.
The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is operating
(TEmn = 1) is shown below.
Figure 6-33. Operation when TOLm Register Has Been Changed Contents during Timer Operation
TOLm
Active Active Active
Active
TO0n (Output)
Set
Reset Set
Reset
Set Reset Set
Reset
Remark 1. Set: The output signal of the TOmn pin changes from inactive level to active level.
Reset: The output signal of the TOmn pin changes from active level to inactive level.
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-34 shows the set/reset operating status where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0
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