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Renesas RL78/G15

Renesas RL78/G15
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RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 516 of 765
Mar 7, 2023
Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4)
ACKE0
Note 4, Note 5
Acknowledgment control
0 Disables acknowledgment.
1 Enables acknowledgment. During the 9th clock period, the SDAA0 line is set to low level.
Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1)
Cleared by instruction
Reset
Set by instruction
STT0
Note 2, Note 6
Start condition trigger
0 A start condition is not generated.
1 When the bus is released (in standby state, when IICBSY0 = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
When communication reservation is enabled (IICRSV0 = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus has been released.
When communication reservation is disabled (IICRSV0 = 1)
The STT0 bit is cleared even if it is set (1), and the STT0 clear flag (STCF0) is set (1). No start
condition is generated.
In the clock stretch state (in master mode):
Releases clock stretching to generate a restart condition.
Cautions concerning set timing
For master reception: Setting this bit to 1 during transfer is prohibited. It can be set to 1 only during the clock stretch
period after the ACKE0 bit has been cleared to 0 and the slave has been notified of final reception.
For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the clock stretch period following the output of the 9th clock.
Setting this bit to 1 at the same time as the stop condition trigger (SPT0) is prohibited.
Once the STT0 bit is set to 1, setting it to 1 again before the clear condition is met is prohibited.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
Setting the STT0 bit to 1 while communication
reservation is prohibited
A loss in arbitration
A start condition is generated by the master
Cleared by LREL0 = 1 (exit from communications)
When IICE0 = 0 (operation stop)
Reset
Set by instruction

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