RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 566 of 765
Mar 7, 2023
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIM0 = 0
ST
STT0 = 1
↓
AD6-AD0
R/W
D7-D0ACK
SPT0 = 1
↓
1
2
3 4 5 6 7
ST AD6-AD0
D7-D0
SPACK R/W ACK ACK
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1
Note 1
)
3: IICS0 = 1000××00B (Clears the WTIM0 bit to 0
Note 2
, sets the STT0 bit to 1)
4: IICS0 = 1000×110B
5: IICS0 = 1000×000B (Sets the WTIM0 bit to 1
Note 3
)
6: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
7: IICS0 = 00000001B
Note 1. To generate a start condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
interrupt request signal.
Note 2. Clear the WTIM0 bit to 0 to restore the original setting.
Note 3. To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
STT0 = 1
↓
SPT0 = 1
↓
1 2 3 4 5
ST AD6-AD0 R/W D7-D0 ST AD6-AD0 D7-D0 SPACK R/W ACKACK ACK
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets the STT0 bit to 1)
3: IICS0 = 1000×110B
4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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