RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 591 of 765
Mar 7, 2023
Note 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition
after a stop condition has been issued is at least 4.0 μs when standard mode is set and at least 0.6 μs when
fast mode is set.
Note 3. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit.
Explanation of <7> to <15> in Figure 13-31 (3) Data ~ data ~ stop condition is given below.
<7> After data transfer is completed, because ACKE0 = 1 for the slave, an ACK is sent to the master by the
hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<8> The master and slave apply clock stretching (SCLA0 = 0) at the falling edge of the 9th clock, and both the
master and slave issue an interrupt (INTIICA0: transfer end interrupt).
<9> The master writes transmit data to the IICA shift register 0 (IICA0) and releases clock stretching by the master.
<10> When the slave reads the received data and releases clock stretching (WREL0 = 1), the master starts to
transmit data to the slave.
<11> After data transfer is completed, an ACK is sent to the master by the hardware of the slave (ACKE0 =1). The
ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<12> The master and slave apply clock stretching (SCLA0 = 0) at the falling edge of the 9th clock, and both the
master and slave issue an interrupt (INTIICA0: transfer end interrupt).
<13> The slave reads the received data and releases clock stretching (WREL0 = 1).
<14> When the master sets a stop condition trigger (SPT0 = 1), the bus data line is cleared (SDAA0 = 0) and the bus
clock line is set (SCLA0 = 1). After the stop condition setup time has elapsed, a stop condition (SDAA0 changes
from 0 to 1 with SCLA0 =1) is generated by the bus data line being set (SDAA0 = 1).
<15> The slave detects the stop condition and issues an interrupt (INTIICA0: stop condition interrupt).
Remark <1> to <15> in Figure 13-31 represent a series of operation procedures for data communications via the I
2
C
bus.
Figure 13-31 (1) Start condition ~ address ~ data shows steps <1> to <6>.
Figure 13-31 (2) Address ~ data ~ data shows steps <3> to <10>.
Figure 13-31 (3) Data ~ data ~ stop condition shows steps <7> to <15>.
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