Chapter 6: I/O Features in Cyclone IV Devices 6–9
OCT Support
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
The R
S
shown in Figure 6–2 is the intrinsic impedance of the transistors that make up
the I/O buffer.
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in each of I/O banks 2, 4, 5, and 7 for Cyclone IV E devices
and I/O banks 4, 5, and 7 for Cyclone IV GX devices. Each calibration block supports
each side of the I/O banks. Because there are two I/O banks sharing the same
calibration block, both banks must have the same V
CCIO
if both banks enable OCT
calibration. If two related banks have different V
CCIO
, only the bank in which the
calibration block resides can enable OCT calibration.
Figure 6–10 on page 6–18 shows the top-level view of the OCT calibration blocks
placement.
Each calibration block comes with a pair of
RUP
and
RDN
pins. When used for
calibration, the
RUP
pin is connected to V
CCIO
through an external 25- ±1% or
50- ±1% resistor for an R
S
OCT value of 25 or 50 , respectively. The
RDN
pin is
connected to GND through an external 25- ±1% or 50- ±1% resistor for an R
S
OCT
value of 25 or 50 , respectively. The external resistors are compared with the
internal resistance using comparators. The resultant outputs of the comparators are
used by the OCT calibration block to dynamically adjust buffer impedance.
1 During calibration, the resistance of the
RUP
and
RDN
pins varies.
Figure 6–2. Cyclone IV Devices R
S
OCT with Calibration
Cyclone IV Device Family
Driver Series Termination
Receiving
Device
V
CCIO
R
S
R
S
Z
O
GND
To Next Page
Loading...
