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Altera Cyclone IV
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1–36 Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Cyclone IV Device Handbook, February 2015 Altera Corporation
Volume 2
Figure 1–35 shows the datapath clocking in the transmitter and receiver operation
mode with the rate match FIFO. The receiver datapath clocking in configuration
without the rate match FIFO is identical to Figure 1–34.
In configuration with the rate match FIFO, the CDR unit in the receiver channel
recovers the clock from received serial data and generates the high-speed recovered
clock for the deserializer, and low-speed recovered clock for forwarding to the
receiver PCS. The low-speed recovered clock feeds to the following blocks in the
receiver PCS:
word aligner
write clock of rate match FIFO
The low-speed clock that is used in the transmitter PCS datapath feeds the following
blocks in the receiver PCS:
read clock of rate match FIFO
8B/10B decoder
write clock of byte deserializer
byte ordering
write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the low-speed clock frequency is halved before
feeding into the write clock of RX phase compensation FIFO. The low-speed clock is
available in the FPGA fabric as
tx_clkout
port, which can be used in the FPGA fabric
to send transmitter data and control signals, and capture receiver data and status
signals.
Figure 1–35. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Non-Bonded Channel Configuration
Notes to Figure 1–35:
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
(1)
Byte Serializer
8B/10B Encoder
Transmitter Channel PCS Transmitter Channel PMA
Serializer
PCIe Hard IP
FPGA
Fabric
PIPE Interface
Tx Phase
Comp
FIFO
tx_datain
tx_dataout
wr_clk rd_clk wr_clk rd_clk
high-speed
clock
low-speed clock
tx_coreclk
tx_clkout
/2
rx_coreclk
Receiver Channel PCS Receiver Channel PMA
rx_dataout
rx_datain
Deserial-
izer
CDR
Byte
De-
serializer
Byte
Order-
ing
Deskew
FIFO
8B/10B
Decoder
Rate
Match
FIFO
CDR clock
/2
(2)
Word
Aligner
Rx
Phase
Comp
FIFO

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