Renesas RL78/G15

RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 181 of 765
Mar 7, 2023
Figure 6-10. Format of Timer Clock Select register m (TPSm) (2/2)
Address: F01B6H, F01B7H (TPS0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm 0 0
PRSm
31
PRSm
30
0 0
PRSm
21
PRSm
20
PRSm
13
PRSm
12
PRSm
11
PRSm
10
PRSm
03
PRSm
02
PRSm
01
PRSm
00
PRSm21 PRSm20 Selection of operation clock (CKm2)
Note 1
f
CLK
(MHz)
1 2 4 8 16
0 0 f
CLK
/2 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
0 1 f
CLK
/2
2
250 kHz 500 kHz 1 MHz 2 MHz 4 MHz
1 0 f
CLK
/2
4
62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz
1 1 f
CLK
/2
6
15.6 kHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz
PRSm31 PRSm30 Selection of operation clock (CKm3)
Note 1
f
CLK
(MHz)
1 2 4 8 16
0 0 f
CLK
/2
8
3.91 kHz 7.81 kHz 15.6 kHz 31.3 kHz 62.5 kHz
0 1 f
CLK
/2
10
977 Hz 1.95 kHz 3.91 kHz 7.81 kHz 15.6 kHz
1 0 f
CLK
/2
12
244 Hz 488 Hz 977 Hz 1.95 kHz 3.91 kHz
1 1 f
CLK
/2
14
61 Hz 122 Hz 244 Hz 488 Hz 977 Hz
Note 1. When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), stop
timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operation clock (f
MCK
) or the valid edge of the signal input
from the TImn pin is selected.
Caution Be sure to clear bits 15, 14, 11, 10 to “0”.