RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 211 of 765
Mar 7, 2023
Remark Figure 6-26 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge
detection becomes 2 f
MCK
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The
error per one period occurs be the asynchronous between the period of the TImn input and that of the count
clock (f
MCK
).
(4) One-count mode operation
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register m (TDRmn) is loaded to the TCRmn register and count
starts.
<5> When the TCRmn register counts down and its count value is 0000H, the interrupt request signal (INTTMmn) is
generated and the value of the TCRmn register becomes FFFFH and counting stops.
Figure 6-27. Operation Timing (In One-count Mode)
TSmn (Write)
TEmn
Start trigger
detection signal
TCRmn
INTTMmn
<4>
<3>
TImn input
Rising edge
f
MCK
(f
TCLK
)
<1>
Edge detection
0000
Initial value
FFFF
0001
m
Start trigger input wait status
<5>
<2>
Remark Figure 6-27 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge
detection becomes 2 f
MCK
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The
error per one period occurs be the asynchronous between the period of the TImn input and that of the count
clock (f
MCK
).
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