RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 257 of 765
Mar 7, 2023
Figure 6-62. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register mn (TMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
CKSm
n1
CKSm
n0
CCSm
n
M/S
Note 1
2
1
0
CISmn
1
CISmn
0
MDmn
3
MDmn
2
MDmn
1
MDmn
0
1/0 1/0 0 0 0/1 0 0 1 1/0 1/0 0 0 1 0 0 1/0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6)
0: Independent channel operation
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
1: 8-bit timer mode
Count clock selection
0: Selects operation clock (f
MCK
).
Operation clock (f
MCK
) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
Note 1. TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0, TMRm5, TMRm7: Fixed to 0
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
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