Renesas RL78/G15

RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 293 of 765
Mar 7, 2023
Figure 6-81. Example of Set Contents of Registers for Two-channel Input with One-shot Pulse Output Function
(Master Channel) (1/2)
(a) Timer mode register 0n (TMR0nH, TMR0nL)
TMR0nH TMR0nL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TMR0n
CKS0n
1
CCS0n
M
Note 1
STS0n
2
STS0n
1
STS0n
0
CIS0n1
CIS0n0
MD0n3
MD0n2
MD0n1
MD0n0
1/0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TI0n pin input edge
00B: Detects falling edge.
Start trigger selection
001B: Selects the TI0n pin input valid edge.
Note 2
Setting of MASTER0n bit (Channel 2)
1: Master channel.
Count clock selection
0: Selects operation clock (f
MCK
).
Operation clock (f
MCK
) selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
Note 1. TMR02: MASTER02 bit
TMR00: 0 fixed
Note 2. A software operation (TS0n = 1) can be used as a start trigger, instead of using the TI0n pin input.
Remark n: Master channel number (n = 0, 2)