Altera Cyclone IV - Page 313

Chapter 1: Cyclone IV Transceivers Architecture 1–33
Transceiver Clocking Architecture
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
Figure 1–31 and Figure 1–32 show the high- and low-speed clock distribution for
transceivers in F324 and smaller packages, and in F484 and larger packages in
non-bonded channel configuration.
Figure 1–31. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F324
and Smaller Packages
Notes to Figure 1–31:
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
Transceiver
Block
GXBL0
MPLL_2
TX PMA
TX PMA
TX PMA
TX PMA
Ch3
(1)
MPLL_1
Ch2
(1)
Ch1
Ch0
(3)
(2)